This invention relates to a semiconductor device and a method of manufacture thereof; in particular, the invention relates to a technique effective when adapted for a semiconductor device having a DRAM (Dynamic Random Access Memory).
As a DRAM structure for achieving higher integration, a Capacitor Over Bitline (COB) structure is conventionally known, wherein a capacitor is disposed over a bit line, a lower electrode (storage electrode) of the capacitor disposed over a bit line is processed into a cylindrical shape, and a capacitative insulating film and an upper electrode (plate electrode) are formed on the lower electrode. The surface area of the lower electrode is enlarged by processing the lower electrode into a cylindrical shape, whereby a reduction in the accumulated charge amount (Cs) of the capacitor caused by the miniaturization of a memory cell can be compensated for. In a memory cell having a COB structure, it is thus inevitable to three-dimensionally form a capacitor structure in order to secure operation reliability as a semiconductor storage device.
However, it has been difficult to secure the necessary capacitance (accumulated charge amount) even in a recent semiconductor device which has been integrated by three-dimensional formation of its capacitor structure, particularly for versions of a DRAM on and after those corresponding to 256 Mbit (mega-bit).
As a technique for further enlarging the area of an electrode, there is a technique using a so-called HSG (Hemispherical Silicon Grain) structure, that is, a technique for forming minute unevenness on the silicon surface on which the lower electrode is formed to provide a roughened surface. According to this technique, the surface area can be enlarged substantially without increasing the size of the lower electrode.
The above-described technique for an HSG structure is however accompanied with the following problems, which are not greatly known, but were discovered only by the present inventors.
Adoption of an HSG structure for a lower electrode makes it possible to enlarge the physical surface area of the lower electrode, but it is accompanied with the problem that an increase in the accumulated charge amount in proportion to the surface enlargement is not always possible. In particular, the problem appears eminently when the lower electrode made of n-type silicon is biased positive toward an upper electrode. This is presumed to be caused by the formation of a depletion layer (by appearance of depletion) on the interface of the lower electrode in contact with a capacitor insulating film. More specifically, adoption of an HSG structure for a lower electrode inevitably requires adoption of silicon as a raw material for it. When a silicon material is employed as a conductor, a large amount of impurities must be introduced. When activated impurities are introduced in a sufficient amount, depletion is suppressed. When the introduced amount of impurities is small or impurities introduced in a large amount are not activated, a depletion layer is formed in the silicon. Since this depletion layer is electrically insulating, it acts like a capacitor insulating film and the apparent thickness of the capacitor insulating film seems to show an increase. This leads to a decrease in the capacitance value of the capacitor, resulting in an increase in the accumulative charge amount which is not proportional to an increase in the surface area of the lower electrode. The decrease in the capacitance value of the capacitor (capacitive loss) reaches at least 30% in terms of a depletion ratio, and such a decrease undesirably becomes a large factor for inhibiting an improvement of refresh properties of the DRAM, thereby inhibiting an improvement of the DRAM performance. In this specification, the depletion ratio is defined as (1xe2x88x92Cxe2x88x92/C+), wherein C stands for a capacitance value when a capacitor is biased toward xe2x88x921V, and C+ stands for a capacitance value when a capacitor is biased toward xe2x88x921V.
As means for avoiding depletion, introduction of impurities in an amount sufficient for compensating for inactivated impurities can be presumed. In order to form an HSG structure, however, it is necessary to subject an amorphous silicon film to predetermined heat treatment, thereby causing solid-phase growth of it into polycrystalline hemispherical crystals. It is needless to say that heat treating conditions (temperature, time, atmosphere, or the like) take part in the growth of crystals from the amorphous state. In addition, an amount of impurities contained in the amorphous silicon, which is a starting material, also takes part in the crystal growth. When a large amount of impurities is contained in the amorphous silicon film, crystallization of amorphous silicon is accelerated excessively, whereby granular silicon (hemispherical crystal) of a sufficient size cannot be formed. The amount of the impurities contained in advance in the amorphous silicon film must therefore be limited and this request for limitation in the amount of impurities is inconsistent with means for suppressing depletion.
Even if the amount of impurities is relatively small so as not to cause a problem in the formation of granular silicon, depletion can be suppressed if these impurities have been sufficiently activated. In other words, it is presumed that depletion can be effectively controlled if impurities contained in the silicon film (lower electrode) after formation of hemispherical crystals have been sufficiently activated (a large portion of impurities contained in the film has been activated). The activation of impurities in silicon however requires heat treatment at a high temperature or for long hours (ex. annealing at a temperature not lower than 800xc2x0 C. or for a time not shorter than 20 minutes). The following problem occurs when the lower electrode is subjected to such high or long heat treatment. When a COB structure is adopted, a capacitor is formed after formation of a bit line. A first interconnection layer of the peripheral circuit is formed simultaneously with the bit line so that a joint part of the first interconnection layer and substrate in the peripheral circuit (ex. source and drain of MISFET of the peripheral circuit) has already been formed in the capacitor-forming stage. At this joint part, a silicide film such as titanium silicide is formed for decreasing the contact resistance. However, this silicide film is poor in heat resistance so that the heat treatment temperature after formation of the first interconnection layer is limited to a low temperature range within the heat resistance of the silicide film. It is therefore impossible to heat-treat the lower electrode of the capacitor at high temperatures for activation of impurities.
Although attention is paid only to the joint part between the first interconnection layer and substrate, high temperature heat treatment is also unsuited for all the members that have already been formed and are poor in heat resistance, for example, an impurity region formed on a semiconductor substrate. In a highly-integrated semiconductor device, impurity diffusion layers (source drain, etc.) are formed while their position and depth are controlled precisely. By the heat treatment at a high temperature or for long hours, impurities in the impurity diffusion layer, which has been formed precisely, are re-diffused, whereby its structure is changed. It is needless to say that such a change puts the original design out of order and adversely affects the properties of the device. In addition, when a p+ gate structure having a boron-implanted gate electrode (polycrystalline silicon film) is adopted, boron is diffused (leaked) by the heat treatment and diffused boron reaches a channel region, which changes the threshold value of the MISFET. This also becomes a factor for deteriorating the properties of the device, thereby lowering the reliability of the semiconductor device.
With the miniaturization of the device to meet requirements for high integration of the DRAM, the size of the area exclusive for the lower electrode also needs to be reduced. In particular, a cylindrical lower electrode needs to have a decreased inner diameter and formation of granular silicon with good precision inside of the miniaturized cylinder is required. In other words, it becomes relatively difficult to control the height (unevenness) of granular silicon owing to the thinning tendency of a polycrystalline silicon film constituting the lower electrode.
An object of the present invention is therefore to provide a technique for controlling depletion of the lower electrode of a capacitor under limited thermal treatment conditions.
Another object of the present invention is to provide a technique for attaining a low depletion ratio in a lower electrode having granular silicon.
A further object of the present invention is to provide a technique suited for control of crystal growth of granular silicon.
A still further object of the present invention is to provide a technique relating to a capacitor having reduced leakage current, thereby improving the reliability of the DRAM.
A still further object of the present invention is to maintain the performance and reliability of a miniaturized semiconductor device on a high level.
The above-described and the other objects and novel features of the present invention will be apparent from the present description and the accompanying drawings.
Among the inventive aspects disclosed in this application, summaries of representative ones will be described briefly.
1. A method of manufacturing a semiconductor device, which comprises (a) depositing an amorphous silicon film and crystallizing it, thereby roughening the surface of the silicon film; (b) crystallizing the whole silicon film thus roughened; and (c) heat treating the silicon film in a gas atmosphere containing an impurity element, thereby introducing the impurity element into the silicon film.
2. A method of manufacturing a semiconductor device, which comprises (a) depositing an amorphous silicon film and crystallizing it, thereby roughening the surface of the silicon film; and (b) heat treating the silicon film in a gas atmosphere containing an impurity element, thereby introducing the impurity element into the silicon film and at the same time, crystallizing the whole silicon film.
3. A method of manufacturing a semiconductor device, which comprises (a) depositing an amorphous silicon film, and (b) heat treating the silicon film to crystallize and roughen the surface thereof, and introducing a impurity-element-containing gas into the heat treating atmosphere after the heat treatment has been started, thereby introducing the impurity element into the silicon film.
4. A method as described above in 3, wherein the roughening reaction of the silicon film is terminated by the introduction of the gas in the step (b).
5. A method of manufacturing a semiconductor device, which comprises (a) depositing an amorphous silicon film, and (b) heat treating the silicon film in an impurity-element-containing gas atmosphere, thereby introducing the impurity element into the silicon film.
6. A method of manufacturing a semiconductor device, which comprises (a) depositing a first amorphous or polycrystalline silicon film, and depositing a second amorphous silicon film, thereby forming a laminated silicon film, (b) crystallizing the second silicon film, thereby roughening the surface of the laminated silicon film, and (c) heat treating the laminated silicon film in an impurity-element-containing gas atmosphere, thereby introducing the impurity element into the laminated silicon film.
7. A method as described above in 6, wherein a natural oxide film is formed between the first silicon film and the second silicon film.
8. A method as.described above in 7, wherein the amount of the impurity contained in the first silicon film is larger than that contained in the second silicon film.
9. A method as described above in any one of 1 to 8, wherein the surface of the silicon or laminated silicon film is cleaned prior to the introduction of the impurity.
10. A method as described above in any one of 1 to 9, wherein after introduction of the impurity, a dielectric film is formed on the silicon or laminated silicon film without being exposed to the air.
11. A method as described above in 10, wherein heat treatment is conducted at 800xc2x0 C. within 15 minutes after the formation of the dielectric film.
12. A method as described above in any one of 1 to 9, wherein after introduction of the impurity, the silicon or laminated silicon film is subjected to heat treatment at 800xc2x0 C. and below within 15 minutes, followed by the formation of a dielectric film on the silicon or laminated silicon film.
13. A method as described above in 12, wherein the surface of the silicon or laminated silicon film is cleaned subsequent to the heat treatment after introduction of the impurity.
14. A method as described above in any one of 1 to 13, wherein the impurity element is phosphorus (P) and heat treatment for introducing the impurity element is conducted within a temperature range of from 500 to 850xc2x0 C. in a gas atmosphere containing phosphine (PH3).
15. A method as described above in 14, wherein the heat treatment for introducing the impurity element is conducted within a temperature range of from 500 to 850xc2x0 C. for 10 minutes or less in a gas atmosphere which contains phosphine (PH3) and hydrogen (H2) and is under reduced pressure.
16. A method as described above in any one of 1 to 15, wherein the amorphous silicon film or the second amorphous silicon film contains an impurity at a concentration not greater than 2.5xc3x971020 atoms/cmxe2x88x923.
17. A method as described above in any one of 1 to 16, wherein a silicide film has been formed on the surface of the semiconductor substrate or polycrystalline silicon film constituting the gate electrode, prior to the step (a).
18. A method as described above in any one of 1 to 17, which further comprises forming a first silicon nitride film on the silicon film or laminated silicon film, wherein the first silicon nitride film is formed by nitriding of the surface of the silicon film or laminated silicon film or depositing a film on the silicon film or laminated silicon film.
19. A method as described above in 18, which further comprises forming a polycrystalline tantalum oxide film on the first silicon nitride film.
20. A method as described above in 19, wherein the step for forming the polycrystalline tantalum oxide film comprises forming a first polycrystalline tantalum oxide film and forming a second polycrystalline tantalum oxide film thicker than the first polycrystalline tantalum oxide film.
21. A method as described above in 19 or 20, wherein the step for forming the polycrystalline tantalum oxide film, first polycrystalline tantalum oxide film or second polycrystalline tantalum oxide film comprises depositing an amorphous tantalum oxide film by CVD and crystallizing the amorphous-tantalum oxide film by heat treatment in an oxidizing atmosphere.
22. A method as described above in 18, which further comprises forming a second silicon nitride film on the first silicon nitride film by CVD.
23. A method as described above in 19, further comprising a step of forming a titanium nitride film by CVD on the dielectric film containing the silicon nitride film, the polycrystalline tantalum oxide film, the second polycrystalline tantalum oxide film or the second silicon nitride film.
24. A method of manufacturing a semiconductor device, which comprises depositing an amorphous silicon film, and crystallizing the surface of the silicon film to roughen the same, wherein the concentration of the impurity contained in the amorphous silicon film is not greater than 2.5xc3x971020 atoms/cmxe2x88x923.
25. A method as described above in 24, wherein the amorphous silicon film is deposited on the underlying polycrystalline or amorphous silicon film and the underlying silicon film contains impurities at a higher concentration than the silicon film.
26. A method as described above in 25, wherein a natural oxide film is formed between the underlying silicon film and the silicon film.
27. A semiconductor device comprising a plurality of MISFETs and capacitors, said capacitors being electrically connected with MISFETs, a first electrode having a roughened surface and being composed of polycrystalline silicon, a second electrode formed opposite to the first electrode and being composed of a metal and an insulating film formed between the first and second electrodes, wherein the depletion ratio of each of the capacitors is not greater than 10%.
28. A semiconductor device as described above in 27, wherein the depletion ratio of each of the capacitors is not greater than 5%.
29. An apparatus for manufacturing a semiconductor device, which comprises a first reaction chamber for depositing an amorphous silicon film on a substrate, a second reaction chamber capable of heat treating the substrate, a vacuum transfer chamber for transferring the substrate into the first and second chambers while maintaining a pressure-reduced condition, a load lock chamber which is connected with the vacuum transfer chamber and conducts loading or unloading of the substrate, wherein subsequent to the deposition of the amorphous silicon film to the substrate in the first reaction chamber, the substrate is transferred into the second chamber, where the surface of the amorphous silicon film is roughened by exposure to a silane gas and heat treatment in the second reaction chamber, and a phosphine-containing gas is introduced into the second reaction chamber to introduce phosphorus into the roughened silicon film while terminating roughening.
30. An apparatus as described above in 29, wherein the substrate is heated up to a temperature at which crystallization of the whole roughened silicon film is conducted in the second reaction chamber.
31. An apparatus as described above in 29 or 30, further comprising a third reaction chamber which permits heat treatment or deposition of a silicon nitride film in an ammonia gas atmosphere and is connected with the vacuum transfer chamber, whereby the substrate is transferred from the second reaction chamber to the third reaction chamber through the vacuum transfer chamber without causing vacuum destruction and a silicon nitride film is formed on the roughened surface of the silicon film in the third reaction chamber.